1. Field of the Invention
The present invention relates to floating gate memory devices, and more particularly to circuits for generating a negative voltage to be applied to a control gate, or other terminal on the memory cell, in such a way that electric field magnitude is controlled across the memory cell for inducing Fowler-Nordheim tunneling.
2. Description of Related Art
Flash memory devices are based on arrays of floating gate memory cells which are programmed in some cases by biasing the memory cells to induce hot electron injection into the floating gate increase the threshold of the memory cell. Also, in many examples the cells are erased by biasing the cells to induce Fowler-Nordheim FN tunneling of electrons out of the floating gate in order to establish a low threshold state. In other cases, FN tunneling is used for both program and erase operations.
One common approach inducing FN tunneling for the erase operation is referred to as source side erase. According to this approach, a negative voltage is applied to the word line of cells in the array to be erased, while a positive voltage or ground, is applied to the source. This biasing establishes an electric field between the floating gate and the source to induce Fowler-Nordheim tunneling. While the gate receives a negative voltage and the source receives a positive voltage or ground, the substrate is grounded and the drain is typically left floating. See U.S. Pat. No. 5,077,691; invented by Haddad, et al.; issued Dec. 31, 1991. In circuits using some cell types, a negative voltage is applied to one of the drain, source or channel to induce charge flow in an opposite direction.
To support the source side erase operation or other negative voltage functions, integrated circuits include a negative voltage charge pump or other source of negative voltage on the integrated circuit. As commented in U.S. Pat. No. 5,077,691, column 2, line 30 to line 68, very high voltages applied at the source of a cell when erasing may result in a relatively high source to substrate current that an on-chip charge pump can not support. When the source voltage is lower, such as that at the supply potential VDD or even lower than VDD, the negative gate bias has to be increased in magnitude accordingly, to ensure that the same vertical field is kept to generate FN tunneling. Also, lower source voltage may help to alleviate the generation of hole trapping at the gate dielectric. Band-to-band tunneling caused by higher source voltage is another unwanted effect.
However, it is found that because of variations in the supply potential VDD of as much as 10% according to industry standards, manufacturing process variations, changes in temperature and variations in current loading on the cells, the voltage applied across the flash cell during erase cannot be maintained in many circumstances to provide predictable erase speed. As a result, the electric field and the effect of a given electric field across the floating gate and source will vary, and the erase time for cells can vary dramatically. There have been some attempts to regulate the negative voltage generation. See for example Venkatesh, et al., "A 55ns 0.35 Micron 5V-Only 16M Flash Memory With Deep-Power-Down" ISSCC 96/Session 2/Flash Memory/Paper TP2.7, pp. 44-45, 1996; and Atsumi, et al., "A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation; IEEE Journal of Solid State Circuits, Vol. 29, No. 4, April 1994.
FIG. 1 illustrates a prior art regulator which roughly speaking compensates for variations in the supply potential VDD. The regulator works with a negative voltage charge pump 500 which applies a negative voltage on line 501. A pair of zener diodes 503 and 504 are connected in series to the drain of p-channel transistor 505. The source of p-channel transistor 505 is connected to the supply potential VDD. The gate of the transistor 505 is driven by the output of comparator 506. The inputs to comparator include a reference voltage V.sub.REF, and the voltage on the node connecting the drain of the p-channel transistor 505 and the cathode of the zener diode 504.
Generally, the circuit of FIG. 1 compensates for supply voltage variations through transistor 505. When the supply potential is higher, the negative voltage on node 501 tends to go more negative. This causes the voltage in the drain of the p-channel transistor 505 to go more negative as well. This will cause the output of the comparator to go lower to allow the node to be pulled up towards the supply potential through the p-channel transistor 505. In this way, the negative voltage can be compensated to have a less negative output. Similarly with a lower supply potential, the voltage on the gate of the transistor 505 is higher causing the voltage on the drain to go lower. This allows a more negative voltage on node 501.
However, it is desirable to provide an improved control over the erase time of flash memory cells, while maintaining the efficiency of the erasing operation.